Publication Type:

Patent

Source:

(2004)

URL:

http://www.google.com/patents/US6756643

Abstract:

<p>A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.</p>

Cite this Research Publication

Dr. Krishnashree Achuthan, Ahmed, S. S., Wang, H. H., and Yu, B., “Dual silicon layer for chemical mechanical polishing planarization”, 2004.

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207
PROGRAMS
OFFERED
6
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
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