This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0. 45 W. © 2012 Science Press, Institute of Electronics, CAS and Springer-Verlag Berlin Heidelberg.
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G. Hegde and Vaya, P., “An efficient 3-dimensional discrete wavelet transform architecture for video processing application”, Journal of Electronics, vol. 29, pp. 534-540, 2012.