This paper presents an efficient Distributive arithmetic (DA) based parallel processor based architecture to realize 3-Dimensional Discrete wavelet transform (3-D DWT) architecture. Basic DA is modified suitably to employ in 3-D DWT. Parallel processing DA architecture employing modified DA algorithm is designed, modeled and implemented on FPGA. The modified DA reduces the storage space and power consumption by 93% and 4% respectively. The parallel processing 3-D DWT architecture realized using modified DA produces a time delay of 65ns and consumes a power of 108mW. The designed parallel processing based 3-D DWT architecture can be used for video processing applications. © 2011 IEEE.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@688180a ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@50e23bdf Through org.apache.xalan.xsltc.dom.DOMAdapter@34c8d6f5; Conference Code:86336
G. Hegde and Vaya, P., “An efficient distributive arithmetic based 3-dimensional discrete wavelet transform for video processing”, in Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, Coimbatore, 2011.