Publication Type:

Journal Article

Source:

International Journal of Applied Engineering Research, Research India Publications, Volume 10, Number 55, p.663-665 (2015)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84942303487&partnerID=40&md5=d9ae6ad9871ef1a44916538cbd64cfa0

Abstract:

Image smoothing has been extensively used for image processing applications such as image restoration. It is used in graphic processing units(GPU) and computer graphics. These GPU’s are used in embedded systems, mobile phones, personal computers and game consoles. Smoothing technique is done using Gaussian filter. In this project non- separable Gaussian smoothers are implemented on an FPGA platform. The use of adder tree makes it area efficient, computationally efficient and fast. So it is observed that for large size images the proposed Gaussian smoother implementation is efficient than the recent one. The architecture is coded in Verilog HDL and the whole design code is synthesized in Xilinx Virtex-5 FPGA, XC5VLX110T-1FF1136. © Research India Publications.

Notes:

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Cite this Research Publication

T. C. Sruthi and S. Murugan, “Efficient implementation of image smoothing in FPGA”, International Journal of Applied Engineering Research, vol. 10, pp. 663-665, 2015.