Publication Type:

Conference Paper

Source:

2017 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2017, Institute of Electrical and Electronics Engineers Inc., Volume 2017-January, p.1349-1355 (2017)

ISBN:

9781509063673

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85042678332&doi=10.1109%2fICACCI.2017.8126028&partnerID=40&md5=94331ee8d264e5fec6c9908e05ac6d99

Keywords:

Advancing technology, Benchmark circuit, built-in self test, Critical problems, Integrated circuit testing, Integrated circuits, Post-bond testing, Scheduling, Scheduling algorithms, Test scheduling, Testing technique, Three dimensional integrated circuits, Timing circuits, VLSI testing

Abstract:

VLSI testing is essential with advancing technology as it helps improve yield and enables the detection of faulty chips after manufacturing. The factors which play important roles are the power dissipation and time taken during the process of testing. BIST, Built-In Self-Test is a testing technique which enables the device to test itself. A reusable BIST is proposed which allows the usage of the same BIST for pre-bond and post-bond testing. The proposed BIST is used for testing 3D stacked ICs. Test scheduling is a critical problem that is faced while 3D stacked ICs are tested as the same tests which are performed during prebond might need to be performed simultaneously or so during post-bond. Here, we propose a modified Skyline algorithm to obtain an improved test schedule. The algorithm is tested on the inputs from ISCAS-85 benchmark circuits. The obtained results are compared with the results from traditional Skyline algorithm.

Notes:

cited By 0; Conference of 2017 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2017 ; Conference Date: 13 September 2017 Through 16 September 2017; Conference Code:133501

Cite this Research Publication

N. Mohan, Krishnan, M., S. Rai, K., Mathu, M. M., and Sivakalyan, S., “Efficient Test Scheduling for Reusable BIST in 3D stacked ICs”, in 2017 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2017, 2017, vol. 2017-January, pp. 1349-1355.