This paper focuses on designing a digital IIR filter using Modified Booth algorithm and using various techniques to improve its functioning. IIR filters require far less multiplications as compared to FIR filters to achieve a frequency response of the same magnitude. Modified Booth algorithm is used as it gives the product of two signed binary numbers in two's complement using radix-4 algorithm which reduces the number of partial products to half as compared to conventional multipliers. Furthermore the performance is enhanced by using pipelining and parallel processing. Pipelining decreases the critical path thus reducing the delay and power of the filter while parallel processing improves the rate of the filter throughput. The design was implemented in Verilog and verified theoretically using MATLAB. Finally power and delay values of a 3-parallel pipelined IIR filter is compared to the power and delay values of the sequential IIR filter in XILINX. © Research India Publications.
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A. Varghese, Vijayan, N. G., Vineeth, K., and Jos, J., “Enhancing power performance of digital IIR Filters using pipelining and parallel processing”, International Journal of Applied Engineering Research, vol. 10, pp. 445-448, 2015.