Publication Type:

Conference Paper


2017 International Conference on Communication and Signal Processing (ICCSP) (2017)


3D parity check code, data bits, Decoding, Digital storage, EDAC method, Encoding, error bits, Error control codes, Error correction, Error correction codes, Error detection, error detection codes, error detection-and-correction, Hamming code, Hamming codes, Hardware design languages, Matrix algebra, matrix format, Memory, parity bits, parity check codes, Power Consumption, Power demand, Reliability, semiconductor memories, Syndrome calculation, Three-dimensional displays


<p>Data stored in memory or buffer needs Error Detection And Correction (EDAC). Errors occur due to supply voltage fluctuations and/or noise due to electromagnetic interference or external radiation. These errors could be either temporary or permanent. In this paper, a EDAC method is proposed to detect and correct errors based on 3D parity check. In the encoder, the data bits are arranged in a matrix format and then parity bits are calculated for each row, column and diagonal. Errors present in parity bits are detected and corrected using Hamming code. Regeneration of data bits and Syndrome calculation at the decoder helps in detecting and correcting the error bits in the data. The 3D Parity check code can correct up to 3 bits of any combination of errors in the data and the Hamming code can correct up to 3 bits in the parity, if they occur in specific combinations. Thus, this method can detect and correct errors in both data and parity bits. This method achieves higher reliability by having a slight tradeoff in area and power consumption compared to other similar methods.</p>

Cite this Research Publication

S. Tambatkar, Menon, S. N., Sudarshan, V., M. Vinodhini, and Dr. N.S. Murty, “Error detection and correction in semiconductor memories using 3D parity check code with hamming code”, in 2017 International Conference on Communication and Signal Processing (ICCSP), 2017.