Due to unremitting scaling down of CMOS technology, huge number of mixed devices is integrated on a chip. For the efficient communication between these devices routers are employed. Buffers are placed on either the input or in the output ports of a Network on Chip router. If a contention occurs in the output physical channel then input port holds the packet temporarily. During a traffic trace only 40% of the buffers are active and rest are left inactive. Power budgets and area requirements of buffers are high. This leads to the motivation for designing a router architecture with shared queues (RoSHAQ). RoSHAQ improves the buffer utilization by sharing of multiple buffers between different ports. In this paper, we projects a 3 dimensional Partial Mesh of Grid topology (PMG)and we use RoSHAQfor our design. We synthesises our topology using Network Simulator-2 tool. Experimental result concludes that PMG has improved performance in terms of latency, throughput and area in comparison with other topologies. © International Science Press.
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Ka Chythanya and Dr. Somasundaram K., “Evaluation of partially connected mesh topology and shared queues router architecture for network on chip”, International Journal of Control Theory and Applications, vol. 9, pp. 4393-4399, 2016.