Publication Type:

Conference Paper

Source:

2004 Spring Meeting of the Material Research Society (2004)

Abstract:

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Cite this Research Publication

J. Barnett, Moumen, N., Gutt, J., Gardner, M., Huffman, C., Majhi, P., Peterson, J. J., Dr. Sundararaman Gopalan, Foran, B., Li, H. J., and , “Experimental study of etched back thermal oxide for optimization of the Si/high-k interface”, in 2004 Spring Meeting of the Material Research Society, 2004.

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