Real-time systems handle data in binary form and these systems should be catered with efficient circuits for fast data accessing and data processing. In this paper, a high speed architecture has been proposed to determine both the value and the address of the maximum/minimum element from an nelement set of k-bit size. The proposed solution performs the data finder and address finder operations in parallel resulting into a low latency and high throughput architecture. This architecture can also be used to determine the total number of occurrences of maximum/minimum with a priority scheme included for the position determination. Synthesis results obtained with 180-nm CMOS standard cell technology for different n and k, show an average of 70% improvement in speed for the proposed architecture when compared with related architectures.
cited By 0; Conference of 6th International Conference on Computer Communication and Informatics, ICCCI 2016 ; Conference Date: 7 January 2016 Through 9 January 2016; Conference Code:121903
S. V. Smrithi and S. Agrawal, “A fast architecture for maximum/minimum data finder with address from a set of data”, in 2016 International Conference on Computer Communication and Informatics, ICCCI 2016, 2016.