<p>This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides crosstalk avoidance and also random and burst error correction up to 5 bits and detection up to 6 bits. The error detection outcomes at all routers in the path are recorded in the error information flit. With the help of error information flit, the error rate is calculated in the destination network interface. The calculated error rate is compared with two threshold values selected based upon the traffic pattern used. If the error rate is less than the lower threshold value, only network layer error control coding scheme is activated. If the error rate is in between the lower and higher threshold values then the error control scheme present in both network layer and datalink layer will be activated, but the error control scheme present in data link layer is activated only in the alternate routers present in the routing path. If the error rate crosses higher threshold value, error control coding scheme present in both the layers will be activated. The proposed JCA-FBEC-SBED error control coding scheme has higher reliability in terms of error detection and correction, when compared to other error control coding schemes with trade-off in delay, area and power consumption. The proposed router architecture has reduced delay and slight increase in area and power consumption of 2.1% and 5.8% respectively, when compared to the runtime adaptive scrubbing router. Our proposed fault tolerant NoC architecture theoretically provide higher data transfer reliability and energy efficiency when compared to other double layer runtime adaptive fault tolerant NoC architectures. The runtime adaptive error control reduces the overall power consumption of the NoC architecture even though JCA-FBEC-SBED decoder consumes more power compared to other schemes. © 2015 IEEE.</p>
cited By 0; Conference of 6th IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015 ; Conference Date: 10 December 2015 Through 12 December 2015; Conference Code:120030
M. Vinodhini, Lillygrace, K., and Dr. N.S. Murty, “A fault tolerant NoC architecture with runtime adaptive double layer error control and crosstalk avoidance”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.