Publication Type:

Patent

Source:

Volume US6224690 B1, Number US 08/614,984 (2001)

URL:

https://www.google.com/patents/US6224690

Abstract:

An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

Cite this Research Publication

P. C. Andricacos, Dr. Madhav Datta, Horkans, W. J., Kang, S. K., Kwietniak, K. T., Mathad, G. S., Purushothaman, S., Shi, L., Tong, H. M., and Deligianni, H., “Flip-chip interconnections using lead-free solders”, U.S. Patent US 08/614,9842001.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
9th
RANK(INDIA):
NIRF 2017
150+
INTERNATIONAL
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