Publication Type:

Conference Paper

Source:

2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, Institute of Electrical and Electronics Engineers Inc. (2015)

ISBN:

9781479979264

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84925652612&partnerID=40&md5=82d985c0cc409bf83ae04ee0ffb8eb4e

Keywords:

Bit error rate, Channel polarizations, code tree, Codes (symbols), Decoding, Encoding (symbols), Field programmable gate arrays (FPGA), Information theory, LDPC, LUT, Polar codes, Random access storage, Successive-cancellation decoding

Abstract:

Polar code, newly formulated by Erdal Arikan, has got a wide recognition from the information theory community. Polar code achieves the capacity of the class of symmetric binary memory less channels. In this paper, we propose efficient hardware architecture on a FPGA platform using Xilinx Virtex VI for implementing the advanced encoding and decoding schemes. The performance of the proposed architecture out performs the existing techniques such as: successive cancellation decoder, list successive cancellation, belief propagation etc; with respect to bit error rate and resource utilization. © 2015 IEEE.

Notes:

cited By 0; Conference of 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 ; Conference Date: 8 January 2015 Through 10 January 2015; Conference Code:111173

Cite this Research Publication

M. S. Oommen and S. Ravishankar, “FPGA implementation of an advanced encoding and decoding architecture of polar codes”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.