Publication Type:

Journal Article

Source:

International Journal of Pure and Applied Mathematics, Academic Press, Volume 118, Number Special Issue 10, p.51-56 (2018)

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85044941656&doi=10.12732%2fijpam.v118i10.7&partnerID=40&md5=ac7060d3b9016137c9e7c70e9e32b16e

Abstract:

<p>Many a times Mathematical computations are easier in frequency domain than time domain. Discrete Fourier transform (DFT) is a tool to convert signals from time domain to frequency domain which is widely used mainly in Digital Signal and Image Processing applications. Fast Fourier Transform (FFT) is a method to find DFT in time constraint applications which is affected by number of complex multiplier. In this paper 16-bit DFT using Vedic Multiplier, a high-speed multiplier is proposed with an objective to replace conventional complex multiplier and to decrease computation time. The proposed system is implemented in Virtex-4 FPGA and the results show that FFT using Urdhva Tiryakbhyam algorithm of Vedic multiplier is faster than other methods of DFT. © 2018 Academic Press. All Rights Reserved.</p>

Notes:

cited By 0

Cite this Research Publication

J. Savithry and N. Prakash, K., “FPGA implementation of DFT processor using vedic multiplier”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 51-56, 2018.