Publication Type:

Journal Article


International Journal of Pure and Applied Mathematics, Academic Press, Volume 118, Number Special Issue 10, p.51-56 (2018)



<p>Many a times Mathematical computations are easier in frequency domain than time domain. Discrete Fourier transform (DFT) is a tool to convert signals from time domain to frequency domain which is widely used mainly in Digital Signal and Image Processing applications. Fast Fourier Transform (FFT) is a method to find DFT in time constraint applications which is affected by number of complex multiplier. In this paper 16-bit DFT using Vedic Multiplier, a high-speed multiplier is proposed with an objective to replace conventional complex multiplier and to decrease computation time. The proposed system is implemented in Virtex-4 FPGA and the results show that FFT using Urdhva Tiryakbhyam algorithm of Vedic multiplier is faster than other methods of DFT. © 2018 Academic Press. All Rights Reserved.</p>


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Cite this Research Publication

J. Savithry and N. Prakash, K., “FPGA implementation of DFT processor using vedic multiplier”, International Journal of Pure and Applied Mathematics, vol. 118, pp. 51-56, 2018.