Publication Type:

Conference Paper


International Conference on Electronics and Communication Systems (ICECS -2014) (2014)



Accession Number:




binary values, Chromosomes, Circuit faults, Computers, Fault diagnosis, fault masking, Filling, filling techniques, fitness value, Genetic algorithm, Genetic algorithms, Integrated circuit testing, Logic gates, multiple stuck-at faults, reordering techniques, Switches, switching activity, Switching circuits, test pattern generation, Test power reduction, VLSI, VLSI circuits


A method of test pattern generation for multiple stuck-at faults in VLSI circuits, using genetic algorithm is proposed. The test patterns were earlier generated for single stuck at faults only but in the proposed work, multiple faults are considered and fault masking is also taken into account when faults are injected. The test patterns to detect the faults are the binary values given as inputs to the circuit under test. These patterns should be compact and also should have minimum switching among them to reduce the test power. Genetic Algorithms (GA) is a search technique to find solutions to optimization and search problems. Hence the proposed work uses GA to generate test patterns. Here the chromosomes in GA are substituted for the test patterns. The test patterns are initialized randomly and their fitness value is evaluated. Now GA operators like selection, crossover and mutation are applied on this initial set to reproduce better test patterns. These generated test patterns are reordered using reordering techniques, don't cares filled by filling techniques to reduce the switching activity among them thus reducing the test power.

Cite this Research Publication

Dr. Anita J. P. and Vanathi, P. T., “Genetic algorithm based test pattern generation for multiple stuck-at faults and test power reduction in VLSI circuits”, in International Conference on Electronics and Communication Systems (ICECS -2014), 2014.