The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. In this paper, we propose and explore multiple architectural options for the <em>HashChip</em>. The <em>HashChip</em> is a hardware architecture aimed at providing a unified solution to the task of message hashing with integrated message padding by aggressive exploitation of similarities in the structure of three commercially popular hash algorithms, namely, MD5, SHA1 and RIPEMD160. A generic approach to prototype digital systems on the Xilinx Virtex 2P embedded FPGA platform is presented and utilized for evaluating the <em>HashChip</em> architectures. The performance of the architectures is studied and evaluated for different design metrics. Throughputs in the range of 200–330 Mbps are obtained on the Xilinx Virtex2P FPGA depending on the input message size and algorithm choice.
T. S. Ganesh, Frederick, M. T., Sudarshan, T. S. B., and Somani, A. K., “Hashchip: A shared-resource multi-hash function processor architecture on FPGA”, Integration, the VLSI journal, vol. 40, pp. 11–19, 2007.