Publication Type:

Conference Paper

Source:

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), IEEE (2001)

URL:

http://ieeexplore.ieee.org/document/934924/?arnumber=934924

Keywords:

-1.5 V, 7.1 angstrom, Annealing, Capacitance, device characteristics, Dielectric substrates, Dielectric thin films, Electrodes, equivalent oxide thickness, gate dielectric applications, Hafnium compounds, Hafnium oxide, HfO/sub 2/ dielectric, HfO/sub 2/-Si, interface reaction, leakage current, MOS capacitors, MOSCAPs, MOSFET, MOSFETs, NH/sub 3/, NH/sub 3/ anneal, NH/sub 3/ nitrided substrates, nitridation, nitridation surface preparation, nitridation technique, nitrogen, Permittivity, quality, Reliability, semiconductor device reliability, surface preparation technique, TaN, TaN electrode, TaN gate electrode, tantalum compounds, temperature, Thermal stability, ultra-thin HfO/sub 2/ gate dielectric MOSFETs

Abstract:

A surface preparation technique using an NH/sub 3/ anneal has been investigated to reduce interface reaction and consequently the equivalent oxide thickness (EOT) of hafnium oxide for alternative gate dielectric applications. MOSCAPs and MOSFETs were fabricated on the NH/sub 3/ nitrided substrates with HfO/sub 2/ dielectric and TaN gate electrode. Using this nitridation technique, EOT of as thin as 7.1 /spl Aring/ with 10/sup -2/ A/cm/sup 2/ at -1.5 V was obtained. Furthermore, excellent device characteristics and reasonable reliability have been achieved.

Cite this Research Publication

R. Choi, Kang, C. Seok, Lee, B. Hun, Onishi, K., Nieh, R., Dr. Sundararaman Gopalan, Dharmarajan, E., and Lee, J. C., “High-quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs with TaN electrode and nitridation surface preparation”, in 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001.

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