Publication Type:

Conference Paper

Source:

Proceedings of 12th IEEE International Conference on Advanced Computing and Communications, Citeseer (2004)

Abstract:

High associativity with replacement policy as LRU is an optimal solution for cache design when miss rate has to be reduced. But when associativity increases, implementing LRU policy becomes complex. As many advance and demanding technologies like multimedia, multithreading, database and low power devices running on high performance processors in servers and work stations use higher associativity to enrich performance, there is a need for designing highly efficient LRU hardware implementations. This paper gives analyses various implementations of the LRU policy for a cache with high associativity. The implementation problems are explored, objectives of the design are identified and various implementations namely Square Matrix, Skewed Matrix, Counter, Link-list, Phase and Systolic Array methods are compared with each other on the basis of objective outlined. These implementations are synthesized to determine the constraints and the effect of increase in associativity on the performance. When the associativity is smaller, reduction of associated logic is important and at higher associativity conservation of space is more important. At higher associativity Linked List, Systolic Array and Skewed Matrix are the designs found suitable for implementations

Cite this Research Publication

T. S. B. Sudarshan, Mir, R. Abbas, and Vijayalakshmi, S., “Highly efficient LRU implementations for high associativity cache memory”, in Proceedings of 12th IEEE International Conference on Advanced Computing and Communications, 2004.

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