Publication Type:

Conference Paper

Source:

Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, p.538-542 (2009)

ISBN:

9781424445196

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-70449134911&partnerID=40&md5=866d8bbd99d869631d66b0bf15d992a0

Keywords:

Cache design, Clock frequency, Clocks, CMOS, CMOS circuits, Computer science, Design, Dual-edged clock, Dynamic Power, Dynamic power dissipation, Electric power utilization, energy consumption, Energy management, Information technology, ON dynamics, Operating frequency, Power efficiency, Power efficient, Power managements, Power requirement, Processor cache, Verilog HDL

Abstract:

Dynamic power dissipation is a major field where various researches have been held to reduce the energy consumption in present clocked systems. Here we discuss the various tiers of power management in design followed by a treatise on dynamic power dissipation in CMOS circuits and power efficient cache designs under research. We further propose a technique in reducing the clock frequency of circuits without compromising the performance. This is achieved by using a dual-edged clock for the operation, allowing the operating frequency to be halved, which immediately translates into a tremendous gain in power efficiency. The applications of this technique in processor caches are also studied. The designs proposed herein were implemented using Verilog HDL and the power requirements analyzed using Xilinx XPower 10.1. Experimental results and the conclusions drawn are included. © 2009 IEEE.

Notes:

cited By 1; Conference of 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009 ; Conference Date: 8 August 2009 Through 11 August 2009; Conference Code:78148

Cite this Research Publication

Rajesh Kannan Megalingam, Krishnan, N., V. Ashok, A., and Arunkumar, M., “Highly power efficient, uncompromised performance cache design using dual-edged clock”, in Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, 2009, pp. 538-542.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS