Publication Type:

Conference Paper

Source:

27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design, IEEE, Mumbai (2014)

ISBN:

9781479925124

URL:

https://www.scopus.com/inward/record.url?eid=2-s2.0-84894593087&partnerID=40&md5=302b1a5b3e61faea693c1d6862395611

Keywords:

Background calibration, Gain error, histogram, Pipelined ADCs

Abstract:

This paper presents a deterministic digital background inter-stage gain calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method first estimates the inter-stage gains of the various stages of the pipelined ADC at power-up by conventional foreground digital calibration technique. It then estimates the maximum digital code at the output of each stage while digitizing the input signal during normal operation. A drift in the interstage gain during normal operation changes the maximum digital code which is estimated by the algorithm. The gain is estimated based on the fact that the ratio of the initial maximum code to the new maximum code is equal to the ratio of the initial gain to the new gain. Since thermal noise can corrupt the accurate estimation of the maximum digital code, an histogram based approach is used to find the maximum code. Unlike other digital background calibration techniques which either require training signals or require the input signal to have certain statistics, simulations show that this technique can accurately estimate the gain for sine wave, ramp, and random inputs having an amplitude as low as 18 dB below full-scale. Simulations also show that this technique is robust to parameter drift and circuit noise. © 2014 IEEE.

Cite this Research Publication

C. Ravi, Rahul, T., and Sahoo, B., “Histogram based deterministic digital background calibration for pipelined ADCs”, in 27th International Conference on VLSI Design, VLSID 2014 - Held Concurrently with 13th International Conference on Embedded Systems Design, Mumbai, 2014.

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