Publication Type:

Conference Paper

Source:

Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2016, Institute of Electrical and Electronics Engineers Inc. (2016)

ISBN:

9781509012770

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84992134096&partnerID=40&md5=7eaeaa865e8222a5f6f6173d9150a34f

Keywords:

Bit error rate, Codes (symbols), Computer circuits, Decoding, Decoding algorithm, Error correction, Error correction capability, LDPC codes, Low-density parity-check (LDPC) codes, Majority logic, One-step majority-logic decoding, Optical communication, Optimal decoding, Reconfigurable hardware, Satellite communication systems, Signal to noise ratio, Sum-product algorithm

Abstract:

A hybrid sub-optimal technique has been proposed in this paper for decoding the LDPC codes, which delivers a better performance. The two decoding algorithms namely, the Sum Product Algorithm (SPA) and One Step Majority Logic Decoding Algorithm (OSMLGD) are pooled together to accomplish decoding of LDPC codes. Also the two algorithms are implemented exclusively in order to compare the performance. The error correction capability is compared by plotting the Bit-Error Rate v/s SNR graph and the computational complexity is also compared. © 2016 IEEE.

Notes:

cited By 0; Conference of 2016 IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2016 ; Conference Date: 18 March 2016 Through 19 March 2016; Conference Code:123144

Cite this Research Publication

S. Neha and Pargunarajan, K., “Hybrid sub-optimal decoding technique for LDPC codes”, in Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2016, 2016.

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