Publication Type:

Conference Proceedings

Source:

2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI) (2019)

URL:

https://ieeexplore.ieee.org/document/8862789

Keywords:

Automatic test pattern generation, Circuit faults, circuit under test, Computer architecture, Design for testability, design for testing, fault coverage, Fault detection, Fault diagnosis, improved test coverage, Integrated circuit testing, LBIST, Logic gates, Observability, observation point, observation point insertion, SCOAP, structural testing, Test coverage, Test pattern generators

Abstract:

Design for testing implies on adding an extra hardware to circuit under test so that the difficulty in testing the circuit becomes easy and large number of faults can be detected to increase the test coverage of the circuit. In a circuit there might be a large number of faults and some fault in the circuit will have high controllability as well as observability those faults will be very difficult to detect. A new approach has been introduced which involves the insertion of observation points at most suitable location to capture the most difficult to observe faults which facilitate structural testing for both on-chip and off-chip for better fault coverage. Insertion of the observation point into the internal part of the circuit enables direct observation of the internal part of the circuit. The observation points are inserted at those locations where observability is high and the occurrence of fault at those location makes the faults hard to propagate to the output.

Cite this Research Publication

V. Veena, Prabhu E., and Mohan, N., “Improved Test Coverage by Observation Point Insertion for Fault Coverage Analysis”, 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI). 2019.