Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO2, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.
G. Bersuker, Gutt, J., Chaudhary, N., Moumen, N., Lee, B. H., Barnett, J., Dr. Sundararaman Gopalan, Brown, G., Kim, Y., Young, C. D., and , “Integration issues of high-k gate stack: Process-induced charging”, in Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International, 2004.