For in–circuit testing and debugging JTAG (Joint Test Access Group) is one of the most powerful standard architecture of DFT (Design For Testability). But JTAG can also act as a tool for hacking and hence makes the devices vulnerable for attacks. This paper presents a Security mechanism for JTAG and hence prevents the unauthorized users from accessing the private and confidential information of a device. This method is highly compatible with the IEEE 1149.1 standard and requires no modification in the Intellectual
Property of an IC. In this paper the standard JTAG Architecture with enhanced security mechanism is described using VHDL.
P. Ajay Kumar, P Kumar, S., and Patwa, A., “JTAG Architecture with Multi Level Security”, IOSR Journal of Computer Engineering, vol. 1, no. 1, pp. 54–9, 2012.