Digital signal processing applications (DSP) algorithms are iterative in nature and computationally intensive. Such computation-intensive procedures are represented by recursive equations and dependence graphs (DGs). Loops are the primary source of parallelism in iterative algorithm. For the purpose of throughput enhancement, loop transformation methods are commonly used in high-level synthesis. One of the most effective transformation techniques, named retiming, is a structural transformation that relocates the delays or registers in a circuit. This reduces the latency of the circuit without changing its functionality. Unfolding is another transformation technique used to improve the throughput of the system which when applied to DSP results in multiple iterations of the original program. Unfolding the program can also unearth buried concurrencies, leading to a drop in the iteration period and a proportionate increase in the throughput. The unfolding transformation is incorporated along with retimed DG to improve the parallel processing of the system. In this paper we have automated the modeling of DG and their transformation using high level language JAVA. The enhanced graphical user interface (GUI) and superior memory allocation system of JAVA make it ideal for such an application and for the realization of RTL generation of the unfolded and retimed DG of the benchmark circuits considered as the next phase of this work.
Dr. Bala Tripura Sundari B. and Preethi, E. S., “Loop transformation for high level synthesis of iterative algorithms”, International Journal of Applied Engineering Research , pp. 31871-31882, 2015.