Publication Type:

Conference Paper

Source:

ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Volume 5, Kanyakumari, p.336-340 (2011)

ISBN:

9781424486779

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-79961232608&partnerID=40&md5=9d28ef948668e24a238388817ae2943d

Keywords:

Algorithms, Clock gating, Computer architecture, Computer hardware, Design, Digital computers, Electric power supplies to apparatus, Iterative CORDIC, Parallel CORDIC, Pipeline processing systems, Pipelined CORDIC, Rotation, Signal processing, Vector rotation

Abstract:

CORDIC (COrdinate Rotation for Digital Computers) is a hardware efficient algorithm that can be used for the implementation of all kinds of digital signal processing architectures used in most of the processing instruments. Today, for most electronic designs, power budget is one of the most important design goals. The paper analyses clock-gating technique, a simple method for power reduction, applied to the different CORDIC architectures and compares their performance especially in three different major styles iterative, parallel and pipelined structures. The core is designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. © 2011 IEEE.

Notes:

cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@2c07f81c ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@3f320cd9 Through org.apache.xalan.xsltc.dom.DOMAdapter@6ee99af8; Conference Code:85884

Cite this Research Publication

R. Bhakthavatchalu and Nair, P., “Low power design techniques applied to pipelined parallel and iterative CORDIC design”, in ICECT 2011 - 2011 3rd International Conference on Electronics Computer Technology, Kanyakumari, 2011, vol. 5, pp. 336-340.