Complex SoC imply the seamless integration of numerous IPs performing different functions and operating at different clock frequencies. The integration of several heterogeneous components into a single system gives rise to new challenges. Major issue includes controlling the clock frequencies of the different modules. As chips become faster and larger, designers face significant challenges including global clock distribution and power dissipation. In-order to achieve global synchronization with high
performance and low power conception globally asynchronous locally synchronous (GALS) method is used. In GALS, local modules can operate with their own clock and the entire module is communicating asynchronously. In this paper we implemented a low power GALS interface with stretchable clocking scheme in verilog HDL and compare the dynamic power of the interface with and without stretchable clocking with Synopsys Design Compiler.
C. Anju and Pande, K. S., “Low Power GALS Interface Implementation with Stretchable Clocking Scheme”, IJCSI International Journal of Computer Science Issues, , vol. 9, no. 4, 2012.