This paper presents a simple model of complex real time MPEG-4 video encoding and decoding using simple techniques in VHDL and MATLAB to provide reasonable compression while using only less power and resources on FPGA. This implementation works on low power and less number of clock cycles. The basic video codec module consists of a video encoder and a decoder. The encoder module consists of blocks for temporal modeling, spatial modeling and Entropy encoding. Temporal block has a difference block whereas spatial block consists of 2-D DCT, Quantizer and a 2-D IDCT. Sample frames of real time video has been processed using the codec module resulting in an average compression of 64.6% It can be applied in areas where low bit rate, high quality video is required. The first 5 sections in this paper represents the concepts and theories used, section 6 onwards represents the actual implementation of the module. © 2009 IEEE.
cited By 0; Conference of 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009 ; Conference Date: 8 August 2009 Through 11 August 2009; Conference Code:78148
A. Prasad, Krishnan, K., Parvathy, K., and Rajesh Kannan Megalingam, “Low power losssless compression of real time mpeg4 video encoding and decoding using vhdl and matlab”, in Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, 2009, pp. 408-412.