In this paper, a low power Encoding and Bypassing technique based shift-add multiplier is presented. The proposed architecture is derived from simple way to reduce power consumption and area of the multiplier in VLSI design architecture level model. The proposed architecture maximum reduces the power consumption and area compared to the other conventional multiplier. The modification to the multiplier includes proposed Encoder design for Modified Radix-4 recording rules, removal of zero partial products using bypassing technique (decoder). A decoder instead of bypass and feeder register is utilized for the removal of zeros (bypassing) and selecting the current partial product value to be stored in register. In this paper, encoder and decoder selector circuit has been used in the proposed model work. Low power consumption and low area occupied multiplier architecture model is proposed. The simulation result for the encoding process and bypassing technique using decoder generated using Xpower analyzer in Xilinx 10.1 ISE (integrated software environment) represents the dynamic power consumption is reduced to almost 50%. When the power consumed by the proposed multiplier using Spartan-2 is 6.28mW, the Virtex-4 device is 6.89mW. The proposed multiplier is mainly applicable for designing low power VLSI circuits and high speed switching techniques. © 2005 - 2013 JATIT & LLS. All rights reserved.
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Prabhu E., Mangalam, H., and Karthick, S., “A low power multiplier using encoding and bypassing technique”, Journal of Theoretical and Applied Information Technology, vol. 57, pp. 251-260, 2013.