Publication Type:

Conference Paper

Source:

2014 International Conference on Embedded Systems (ICES) (2014)

Keywords:

accuracy, Benchmark testing, cache storage, data cache behavior, embedded applications, embedded system, Embedded systems, energy conservation, energy consumption, Energy efficiency, Ice, instruction cache behavior, Low power Cache memory design, low power predictive placement cache scheme, Mibench embedded benchmark, Mibench embedded benchmarks, minimal prediction bits, Pipelines, power aware computing, Power Consumption, Prediction algorithms, Predictive placement, Set associative cache, Simplescalar 3.0 simulator

Abstract:

The power consumption is crucial for embedded applications which are operated by battery. This paper compares the behavior of instruction cache and data cache of predictive placement scheme using minimal prediction bits on energy efficiency and performance. The performance of predictive placement scheme is evaluated and compared with Way Prediction for instruction cache and data cache. Using proposed scheme, an average energy saving of 71.6% for data cache and 64% for instruction cache can be achieved over conventional set-associative cache scheme. Simplescalar 3.0 simulator is used to obtain the results for Mibench embedded benchmarks

Cite this Research Publication

Bhargavi R. Upadhyay and Sudarshan, T. S. B., “Low Power Predictive Placement Cache Scheme for Embedded System”, in 2014 International Conference on Embedded Systems (ICES), 2014.

207
PROGRAMS
OFFERED
6
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS