Publication Type:

Conference Paper

Source:

2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016, Institute of Electrical and Electronics Engineers Inc. (2017)

ISBN:

9781509006113

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85019995888&doi=10.1109%2fICCIC.2016.7919529&partnerID=40&md5=8565df97f79bdcf124d846e69b662b47

Keywords:

90 nm technology, Analog design, Artificial intelligence, CMOS integrated circuits, Computation theory, Delay circuits, Existing architectures, HCPM, Low power electronics, Low power vlsis, Manchester, Modified GDI, Reusability, Signal encoding, Sols, VLSI architectures, VLSI circuits

Abstract:

The VLSI architecture for the low power combined FM0 and Manchester encoder (SOLS) circuit using modified GDI has been proposed in this paper. Comparisons are made with existing architecture using general CMOS Logic. The power consumption and delay in this circuit are reduced. The working conditions for existing circuit for FMO/Manchester encoder and decoder using HCPM technique have also been modified in this paper. The architecture has been realized in CMOS 90 nm technology. Cadence Virtuoso Analog design environment has been used for implementing and synthesizing the test circuits. © 2016 IEEE.

Notes:

cited By 0; Conference of 2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016 ; Conference Date: 15 December 2016 Through 17 December 2016; Conference Code:127661

Cite this Research Publication

N. Sowjith, K. Sandeep, S., Sumanth, M., and S. Agrawal, “Low power VLSI architecture for combined FMO/Manchester encoder for reusability and FMO/Manchester codecs”, in 2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016, 2017.

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