Publication Type:

Conference Paper


2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), IEEE, Berlin; Germany (2014)



Computer architecture, design under test, DUT, Embedded systems, hard-real-time embedded systems, Hardware, hardware-in-loop testbed, HIL, MAESTRO, modular architecture with event-driven synchronization and time-driven real-time operations, Monitoring, product development life-cycle, program testing, program verification, Real-time systems, robust embedded testbed, Schedulability, Scheduling, Software, software verification, synchronisation, Testing, time-driven embedded testbed architecture, Vectors


In the product development life-cycle of hard-real-time embedded systems, software verification plays a very important role. During verification, a Hardware-In-Loop (HIL) testbed is used to test the key properties of the software, namely, schedulability, concurrency and timeliness, by exercising and monitoring the interfaces of the Design Under Test (DUT). Often, building a testbed to test these properties can be challenging and costly. For the first time, this paper proposes a Modular Architecture with Event-driven Synchronization and Time-driven Real-time Operations (MAESTRO) for a low-cost testbed, to support HIL and system testing. Our proposed MAESTRO-based testbed is compared with other testbeds and is shown to provide superior performance. Finally, the paper also defines key properties essential for building a robust embedded testbed.

Cite this Research Publication

S. Karunagaran, Sahoo, K. P., Jayaraj Poroor, and Fujita, M., “MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization”, in 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), Berlin; Germany, 2014.