Publication Type:

Conference Paper

Source:

2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, Institute of Electrical and Electronics Engineers Inc. (2015)

ISBN:

9781479978489

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84965062142&partnerID=40&md5=51b53f09b29cff463c00a00a12e9d3cf

Keywords:

Artificial intelligence, Authentication, Bit error rate, De-scrambling, Electric power utilization, Graphical user interfaces, Linear feedback shift registers, Memory architecture, Nonlinear feedback, Nonlinear feedback shift registers, Program compilers, Scrambling, Security and NIST test suite, Shift registers, User interfaces

Abstract:

<p>In this paper, memory architecture for ensuring data security is proposed. A Graphical User Interface (GUI) is assumed in the work to enter user ID and password for each user authentication. Valid user will be given access to the corresponding data whereas invalid user will be given access but will receive garbage data to prevent multiple trails to break in. The architecture using Galois type Linear Feedback Shift Registers (LFSRs) as well as Nonlinear Feedback Shift Registers (NLFSRs) is implemented and verified for the functionality. The power consumption is estimated using 180nm Cadence RTL Compiler and the level of data security using the National Institute of Standards and Technology (NIST) test suite for random numbers and compared the results achieved through the two implementations. The power consumption is 2.291 mW for NLFSR type of implementation and is less than that of the LFSR type of implementation by 23.9%. It is observed that NLFSR type of implementation passes the four NIST tests and whereas the LFSR type of implementation fails in two out of the four NIST tests. © 2015 IEEE.</p>

Notes:

cited By 0; Conference of 6th IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015 ; Conference Date: 10 December 2015 Through 12 December 2015; Conference Code:120030

Cite this Research Publication

J. Jose, Pande, K. S., and Dr. N.S. Murty, “A memory architecture using linear and nonlinear feedback shift registers for data security”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

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