In this paper, we propose a Network on Chip router architecture with increased reliability, energy efficiency and with reduced area overhead. The proposed router architecture model adjusts dynamically to the error control strengths of the layers of NoC. In this paper, we target to optimize the combined operations of arbiter and multiplexer by using a Merged Arbiter Multiplexer (MARX) along with a dual layer cooperative error control protocol. By doing so, the number of pipe line stages, area and power consumed is reduced. We use XY Routing algorithm to send data from one router to the other when these routers are placed in network architecture. The proposed model outperforms the dual layer error control model without MARX unit. The router architecture with MARX unit has 22.7% less area and 2.4% less energy consumption than router architecture without MARX unit but has moderate increase in the delay. © 2015 IEEE.
cited By 0; Conference of 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015 ; Conference Date: 8 January 2015 Through 10 January 2015; Conference Code:111173
Ha Kalwad, Neeharika, Sb, Divya, Sc, M. Vinodhini, and Dr. N.S. Murty, “Merged switch allocation and transversal with dual layer adaptive error control for Network-on-Chip switches”, in 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015.