Publication Type:

Miscellaneous

Source:

(2004)

URL:

http://www.google.co.in/patents/US6770523

Abstract:

A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

Cite this Research Publication

K. S. Sahota, Erhardt, J. P., Halliyal, A., Van Ngo, M., and Achuthan, K., “Method for semiconductor wafer planarization by CMP stop layer formation”. 2004.

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