Publication Type:



Volume US7052969 B1, Number US 10/190,002 (2006)



<p>A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer.</p>

Cite this Research Publication

K. S. Sahota and Dr. Krishnashree Achuthan, “Method for semiconductor wafer planarization by isolation material growth”, U.S. Patent US 10/190,0022006.

It appears your Web browser is not configured to display PDF files. Download adobe Acrobat or click here to download the PDF file.