Publication Type:






Shallow trench isolation techniques are disclosed in which a thin nitride layer is formed on a semiconductor substrate, and a trench is formed through the nitride layer and into the semiconductor substrate, which is then filled. The wafer is then planarized using a fixed-abrasive CMP process to mitigate or avoid step height in the shallow trench isolation process. The nitride layer is then removed following planarization

Cite this Research Publication

K. Sahota and Dr. Achuthan, K., “Methods for reduced trench isolation step height”, 2003.