Publication Type:

Conference Paper

Source:

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), IEEE, Volume 2016-September, p.508-511 (2016)

URL:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7560249

Keywords:

Algorithm design and analysis, analogue-digital conversion, Capacitance, Capacitors, circuit optimisation, closed form expressions, geometric programming (GP), Integer programming, MINLP based power optimization, mixed integer nonlinear programming (MINLP), mixed integer nonlinear programming based optimization algorithm, network synthesis, nonlinear programming, objective function, Operational amplifiers, Optimization, pipelined ADC, Power Consumption, Power demand, power optimized pipelined ADC design, PROGRAMMING, sampling capacitor, stage resolution, total power consumption minimization, word length 10 bit, word length 12 bit, word length 16 bit

Abstract:

This paper proposes a Mixed Integer Non-linear Programming (MINLP) based optimization algorithm to design power optimized pipelined ADC. For a given specification the proposed algorithm gives stage resolution and sampling capacitor per stage that minimizes the total power consumption. Closed form expressions of the power consumption of each stage were derived and used as objective function. Pipelined ADCs of various specifications, viz., 10-bit, 12-bit, and 16-bit, were designed and validated using this algorithm.

Notes:

cited By 0

Cite this Research Publication

Dr. Purushothaman A., “MINLP Based Power Optimization for Pipelined ADC”, in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, vol. 2016-September, pp. 508-511.

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