Fast Fourier Transforms, popularly known as FFTs, have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily Area, Memory and Speed. The aim is to build a Reconfigurable Fast Fourier Transform Block which is suitable for any signal processing application, especially for communication blocks such as OFDM receivers. The objective is to design an FFT block that is capable of computing any N-point FFT and employs R2SDF (Radix 2 Single Delay Feedback) architecture with a single ROM. The design has been developed using the hardware description language VHDL on Xilinx xc5vlx110t. The result shows significant reduction in area for this architecture. © 2013 IEEE.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@87f788b ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@68c2f208 Through org.apache.xalan.xsltc.dom.DOMAdapter@56a020f3; Conference Code:97801
Dr. Ramesh Bhakthavatchalu, Kripalal, A., Nair, S., Venugopal, P., and Viswanath, M., “Modified FPGA based design and implementation of reconfigurable FFT architecture”, in Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013, Kerala, 2013, pp. 818-822.