Publication Type:

Conference Paper

Source:

2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), IEEE, Madurai,India (2015)

Accession Number:

15870687

URL:

http://ieeexplore.ieee.org/abstract/document/7435695/

Keywords:

1-D DWT, 1D discrete wavelet transform, Adders, channel bank filters, Computer architecture, Discrete wavelet transforms, DWT, Filter Bank Approach, Filter banks, Finite impulse response filters, FPGA, Hardware, MAC loop based filter, MLBF, Modelsim, poly-phase structure, Virtex-6 XC6VCX240T-2FF784 target device, Xilinx ISE 14.2

Abstract:

This work proposes an architecture for fast computation of 1-D Discrete Wavelet Transform (DWT). Existing MAC loop based filter (MLBF) is modified and a poly-phase structure for 1-D DWT is proposed. Proposed structure improves the throughput by 1.5x while using almost double the hardware as that of the existing structure. 1-D DWT using existing MLBF structure and proposed structure are simulated using ModelSim and synthesized using Xilinx ISE 14.2 on Virtex-6 XC6VCX240T-2FF784 target device. It is observed that the proposed architecture can be operated at a maximum frequency of 163.59MHz. The simulation results obtained from ModelSim is compared with MatLab R2010a output and found to be accurate.

Cite this Research Publication

S. V. B. Bala Sai, Mamatha, I., Dr. Shikha Tripathi, and Sudarshan, T. S. B., “Modified MLBF based architecture for 1-D DWT”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai,India, 2015.

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