Today's electronic systems, with ever-growing demand for mobile computing devices, are more complex, fast and energy efficient. Cost and quality are the major issues in testing these circuits. The test data storage requirements, along with the operating frequency and channel capacity, have a significant impact on the test cost. This paper presents a new compression scheme based on Alternating Variable Run-length (AVR) codes for reducing the test data. Weighted transition based reordering scheme is adopted prior to the compression scheme to improve the compression ratio (CR). By applying an appropriate mapping scheme, sufficient reduction in power has been achieved. The scheme is also found to have a maximum of 10% increase in compression ratio when compared to the conventional frequency directed run-length codes (FDR) codes and extended FDR (EFDR) codes without any significant on-chip area overhead. The experiments are performed on ISCAS'89 benchmark circuits. © 2012 Springer-Verlag.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@1f0200f0 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@3c8b9c77 Through org.apache.xalan.xsltc.dom.DOMAdapter@71cd67ae; Conference Code:91382
P. R. Sruthi and Dr. Nirmala Devi M., “A modified scheme for simultaneous reduction of test data volume and testing power”, Sixteenth International Symposium on VLSI Design and Test (VDAT 2012, vol. 7373 LNCS, pp. 198-208, 2012.