MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics

Publication Type:

Conference Paper

Authors:

L. Kang; K. Onishi; Y. Jeon; Byoung Hun Lee; C. Kang; Wen-Jie Qi; R. Nieh; Dr. Sundararaman Gopalan; R. Choi; J. C. Lee

Source:

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), IEEE (2000)

URL:

http://ieeexplore.ieee.org/document/904253/?arnumber=904253&tag=1

Keywords:

Annealing, crystallization, Dielectric thin films, dopant activation, dual polysilicon gate, Electrodes, equivalent oxide thickness, Hafnium compounds, Hafnium oxide, HfO/sub 2/-Si, High K dielectric materials, High-K gate dielectrics, leakage current, MOS capacitors, MOSCAP, MOSFET, MOSFET circuits, output current, self-aligned processing, Semiconductor films, single-layer HfO/sub 2/ high-K dielectric thin film, subthreshold swing, temperature

Abstract:

MOSFETs and MOSCAPs of a single-layer thin HfO/sub 2/ gate dielectric with dual polysilicon gate were fabricated with self-aligned process and characterized. Polysilicon and dopant activation processes were optimized such that leakage current and equivalent oxide thickness (EOT) of HfO/sub 2/ remain low (EOT of 12.0 /spl Aring/. HfO/sub 2/ with 1/spl times/10/sup -3/ A/cm/sup 2/ at Vg=1.0 V). Reasonable N- and P-MOSFET characteristics such as subthreshold swing of 74 mV/decade and output currents were also demonstrated.

Cite this Research Publication

L. Kang, Onishi, K., Jeon, Y., Lee, B. Hun, Kang, C., Qi, W. - J., Nieh, R., Dr. Sundararaman Gopalan, Choi, R., and Lee, J. C., “MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics”, in International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000.

 
          
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