Publication Type:

Conference Paper

Source:

2011 IEEE International Symposium of Circuits and Systems (ISCAS) (2011)

Keywords:

accuracy, analog IP test, analog voltage delay controls, clock signal pair, Clocks, CMOS analogue integrated circuits, current starved inverters, current-starved, delay, delay cells, integrated circuit measurement, Integrated circuit testing, invertors, low bandwidth signals, low bandwidth voltage measurement, mostly-digital analog scan-out chain, on-chip analog voltage measurement method, quantization, sampling methods, semiconductor device measurement, size 130 nm, Sub-sampling, sub-sampling technique, Temperature measurement, UMC CMOS process, Voltage measurement

Abstract:

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Cite this Research Publication

Dr. Rajath Vasudevamurthy, Das, P. K., and Amrutur, B., “A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test”, in 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011.

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