Publication Type:

Conference Paper

Source:

2009 NORCHIP (2009)

URL:

http://ieeexplore.ieee.org/abstract/document/5397832/

Keywords:

communication networks, Communication system traffic control, congestion minimization, Councils, destination node, Information technology, Mathematics, Minimization methods, multidimensional routing algorithms, multiple paths, Network on Chip, Network routing, Network-on-a-chip, Network-on-chip, Resource allocation, resource allocation problems, routing, single path, source node, Switches, System recovery, Wireless sensor networks

Abstract:

In network on chip (NoC), the traditional routing schemes are routing the network through a single path or multiple paths from one source node to a destination node, which will minimize the congestion in the routing architecture. Though these routing algorithms are moderately efficient, but time dependent. To reduce overall data packet transmission time in the network, we consider a network with multiple sources and multiple destinations. Multi-dimensional routing problems appear naturally in several resource allocation problems, communication networks and wireless sensor networks. In this paper, we have shown a multi-dimensional path routing algorithm for minimizing the congestion in NoC with deadlock free.

Cite this Research Publication

Dr. Somasundaram K. and Plosila, J., “Multi-dimensional routing algorithms for congestion minimization in Network-on-Chip”, in 2009 NORCHIP, 2009.

207
PROGRAMS
OFFERED
6
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS