Publication Type:

Conference Paper

Source:

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems (2013)

Keywords:

accuracy, Clocks, CMOS integrated circuits, Deep sub-micron, deep submicron processes, deep-sub-micron CMOS processes, delay, delay measurement, Delays, integrated circuit measurement, Integrated circuit testing, Inverters, Matlab-Simulink, mixed-signal, multiphase input clock scheme, multiphase technique, Phase measurement, Radiation detectors, sampling methods, small fixed test delays, SNR, Sub-sampling, subsampling approach, VLSI, VLSI circuits

Abstract:

A multi-phase technique for speeding up the measurement of delays via sub-sampling is presented. Measurement of delays using the sub-sampling approach leads to a very simple system implementation, and also provides the opportunity of trading off between bandwidth and accuracy. Such a scheme becomes extremely attractive for deep sub-micron processes due to its highly-digital nature and the ability to offer compact, low power, mixed-signal implementation alternatives. However, a drawback is the amount of averaging (measurement time) that is needed to get accurate results. A multiphase input clock scheme is proposed to address this issue, especially for the measurement of small delays, thereby speeding up the overall measurement. Simulation results from MATLAB Simulink confirm the speedup achieved upto a factor of eight with an eight-phase clock input for sufficiently small fixed test delays and also an improvement in SNR upto 11dB for slowly varying test delays.

Cite this Research Publication

Dr. Rajath Vasudevamurthy and Amrutur, B., “Multiphase Technique to Speed-up Delay Measurement via Sub-sampling”, in 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013.

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