Publication Type:

Conference Paper


2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur (2010)





AD test, ATPG, Boolean satisfiability, Diagnosis, Diagnosis methods, Fault location, Formal logic, Initial faults, Multiple fault diagnosis, Multiple faults, Path tracing, Primary outputs, SAT solvers, Single-location at-a-time, SLAT, Test vectors, Testing, VLSI circuits


<p>In this paper,a new techniques is proposed for diagnosing multiple faults in a given erroneous circuit with improved diagnosis resolution. The first techniques is based on Single Location At a Time (SLAT) and path tracing techniques which start with an initial fault list obtained from an existing diagnosis method. The single observation - single location at a time (SOSLAT) pattern of a fault will detect that fault at one primary output such that other fault in the list will not mask the fault at that primary output. This can be achieved by deactivating the faults that can be propagated to that particular primary output The second technique follows a Boolean Satisfiability (SAT) based diagnosis. A special kind of test called the Anti-Detecting test (AD) is performed. The AD test restricts the number of test vectors improving the diagnosis time. A SAT based diagnosis is done by converting these test vectors into a set of constraints and solving test using a SAT solver. The solution gives the values of the select lines of the multiplexers (induced as a part of SAT diagnosis) inserted at the fault location of the fault list, indicating the presence or absence of the fault. The above two techniques can be applied together for improved diagnosis resolution and time. ©2010 IEEE.</p>


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Cite this Research Publication

Dr. Anita J. P. and Vanathi, P. T., “Multiple fault diagnosis with improved diagnosis resolotion for VLSI circuits”, in 2010 2nd International Conference on Computing, Communication and Networking Technologies, ICCCNT 2010, Karur, 2010.