Publication Type:

Journal Article

Source:

Sadhana - Academy Proceedings in Engineering Sciences, Volume 38, Number 4, p.645-651 (2013)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84886510311&partnerID=40&md5=667e391067ecad8099ba6e6dc8f88345

Keywords:

Berkeley predictive technology models, CMOS integrated circuits, Dynamic power control, Energy efficiency, Koomey's law, Low Power, NAND gate, pass-transistor, Process Technologies, System-on-chip applications, VLSI circuits

Abstract:

This paper formulates a new design technique for an area and energy efficient Universal NAND gate. The proposed robust three transistors (3T) based NAND gate is just as effective for dynamic power control in CMOS VLSI circuits for System on Chip (SoC) applications. The 3T NAND gate is intuitively momentous and lead to better performance measures in terms of dynamic power, reduced area and high speed while maintaining comparable performance than the other available NAND gate logic structures. Simulation tests were performed by employing standard Berkeley Predictive Technology Model (BPTM) 22 nm, 45 nm and 90 nm process technologies. The experiment and simulation results show that, the proposed 3T NAND gate effectively outperforms the basic CMOS NAND gate with excellent driving capability and signal integrity with exact output logic levels. © 2013 Indian Academy of Sciences.

Notes:

cited By (since 1996)0

Cite this Research Publication

MaGeetha Priya and Baskaran, Kb, “A new universal gate for low power SoC applications”, Sadhana - Academy Proceedings in Engineering Sciences, vol. 38, pp. 645-651, 2013.

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