Publication Type:

Conference Paper

Source:

Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, p.290-295 (2011)

ISBN:

9780769544472

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-80052593525&partnerID=40&md5=ffb21b3b6ccff13001fc60ef4752b8df

Keywords:

Behavioral synthesis, Data flow analysis, Design, Electric power supplies to apparatus, Evolutionary computations, Genetic algorithms, Graphic methods, High Level Synthesis, Low-power design, Multi objective, Multiobjective optimization, System level design

Abstract:

<p>The use of multi-objective approaches in High Level Synthesis has been gaining lot of interest in recent years since the major design objectives such as area, delay and power are mutually conflicting, thereby necessitating trade-offs between different objectives. This paper proposes a methodology for area, power and delay optimization using the Non-dominated Sorting Genetic Algorithm II (NSGA II). A metric based technique has been used to determine the likelihood of a schedule to yield low power solutions during binding. Actual power numbers are not determined since this is computationally expensive. The methodology has been evaluated on standard benchmark Data-Flow Graphs (DFGs) and results indicate that it yields improved solutions with better diversity when compared to a weighted sum GA approach. For the IIR benchmark, it was observed that the NSGA II was able to converge to the true Pareto front obtained from exhaustive search. © 2011 IEEE.</p>

Notes:

cited By (since 1996)1; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@5affb9a7 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@4af5b19d Through org.apache.xalan.xsltc.dom.DOMAdapter@485fe0dd; Conference Code:86442

Cite this Research Publication

S. Harish, Bhuvaneswari, M. Cb, and Logesh, S. Ma, “A novel evolutionary technique for multi-objective power, area and delay optimization in High Level Synthesis of datapaths”, in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, Chennai, 2011, pp. 290-295.