DCT/IDCT finds potent application in the field of image and signal processing. In this paper we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low power implementations as in , but in this novel implementation we prove that a lower power implementation can be done which also increases speed (of what?) by approximately five times over that of conventional implementations. The implementation of both non-pipelined (conventional) and pipelined method uses Xilinx XC3S4000 FPGA. The DCT/IDCT is found using the most common and optimum method of taking inputs as set of eight data elements , . Finally, a comparison of the speeds of both implementations is made, and the speed up achieved by the low power pipelined implementation of 1D-DCT/IDCT is presented. © 2009 IEEE.
cited By 2; Conference of 2009 International Conference on Computer Technology and Development, ICCTD 2009 ; Conference Date: 13 November 2009 Through 15 November 2009; Conference Code:79880
Rajesh Kannan Megalingam, Vineeth, S. V., Venkat, K. B., Mithun, M., and Srikumar, R., “Novel low power, high speed hardware implementation of 1D DCT/IDCT using Xilinx FPGA”, in ICCTD 2009 - 2009 International Conference on Computer Technology and Development, Kota Kinabalu, 2009, vol. 1, pp. 530-534.