Publication Type:

Journal Article

Source:

International Journal of Electronics, Volume 100, Number 10, p.1429-1440 (2013)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84881292214&partnerID=40&md5=9459df4ec4977b5d8687dfa3a57a30c3

Keywords:

3-DDWT, Application specific integrated circuits, Computing techniques, Daubechies filters, Discrete wavelet transforms, Filter banks, Image coding, Low-power consumption, Parallel architectures, Pipe linings, Proposed architectures, Real-time video compression, Storage requirements, Taiwan semiconductor manufacturing companies, Video signal processing

Abstract:

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9, 7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65 nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486 MHz with a power consumption of 2.56 mW. This architecture is suitable for real-time video compression even with large frame dimensions. © 2013 Taylor and Francis Group, LLC.

Notes:

cited By (since 1996)0

Cite this Research Publication

G. Hegde and Vaya, P., “A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding”, International Journal of Electronics, vol. 100, pp. 1429-1440, 2013.

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